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Table 2-2 · Technology-Specific Source Files
FPGA Specific Files
bibufpad
cbe_par
cm8d
cm8dp
cm8dx
cm8dx2
cm8dx3
cm8dxe
cm8x
coreclocks
datapath_registers
del_buff
family
inbufpad
mux4_8
outputpad
ram64x32
Miscellaneous Files
pcicoretest
loopback
pcicore_components
Description
This module contains a bidirectional I/O pad.
This block implements a PCI parity generator and checker. The 36-input parity tree is hand-optimized to
obtain the most efficient implementation for each FPGA family.
This is a low-level FPGA technology cell implementing a four-input multiplexer and register with clear.
This is a low-level FPGA technology cell implementing a four-input multiplexer and register with preset.
This is a low-level FPGA technology cell implementing a four-input multiplexer and register with clear.
This is a low-level FPGA technology cell implementing a four-input multiplexer and register with clear, with
some inputs tied or shared.
This is a low-level FPGA technology cell implementing a four-input multiplexer and register with clear, with
some inputs tied or shared.
This is a low-level FPGA technology cell implementing a four-input multiplexer and register with enable and
clear.
This is a low-level FPGA technology cell implementing a four-input multiplexer.
This module contains the global and clock buffers.
This module implements the datapath registers used to interface to the PCI bus.
This module contains a delay element used to insert delays to control the PCI hold times. The amount of
inserted delay for all critical PCI input paths can be adjusted in this file.
This is a VHDL package or Verilog include file that sets the FPGA family to enable some family-specific
optimizations.
This module contains an input I/O pad.
This is a low-level FPGA technology cell implementing eight four-input multiplexers.
This module contains an output I/O pad.
This module contains a 64×32 RAM using the appropriate FPGA memory blocks.
Table 2-3 · CorePCIF Miscellaneous Source Files
Description
This is a top-level wrapper module that creates a simple top-level design with just the PCI I/O pins used for
creating the example layout databases in the release. It connects all PCI interface signals to top-level ports, and
then all interface signals to the loopback module.
This module is used in the example database designs. It connects core backend output signals to input signals.
This removes the need for the backend signals to be connected to FPGA I/O pins when creating the example
designs, allowing the core to be placed and routed in small pinout packages.
This is a VHDL components package that contains the PCI core component declaration.
v4.0
27
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COREPCIF-RMFL 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
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